NetworkSim.system_verilog.transmitter.generate_testvector

NetworkSim.system_verilog.transmitter.generate_testvector(simulator, transmitter_id=1, id_width=7, address_width=8, data_width=128, output_dir=None)[source]

Testvector generation for transmitters.

Parameters
  • simulator (BaseSimulator) – The simulator used for testvector generation.

  • transmitter_id (int, optional) – The ID of the transmitter of choice, by default 1

  • address_width (int, optional) – The bit width of transmitter RAM address, by default 8

  • data_width (int, optional) – The bit width of the transmitter RAM data, by default 128

  • output_dir (str, optional) – Output directory for the testvectors, by default None (the testvectors directory under Digital-Design).

  • bidirectional (bool, optional) – If bi-directional transmission scheme is carried out. Default is False.

Returns

ram_content_tv, data_out_tv – Two lists (or four lists in the case of bi-directional transmission) containing RAM content and output data signal to be checked against.

Return type

list